A RECONFIGURABLE SYSTEM FOR DIGITAL SIGNAL PROCESSING

被引：0
|
作者：
Letian, Huang [1 ]
Guangfun, Li [1 ]
机构：
[1] UESTC, Sch Commun & Informat Engn, Chengdu 610054, Sichuan, Peoples R China
来源：
2008 5TH INTERNATIONAL MULTI-CONFERENCE ON SYSTEMS, SIGNALS AND DEVICES, VOLS 1 AND 2 | 2008年
关键词：
reconfiguration system; digital signal processing; algorithms; cell; multiplier;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Commonality of various algorithms is analyzed based on the research of algorithms commonly used digital signal processing and a reconfigurable cell is proposed. A reconfigurable system with the cells is designed, which is widely used in a variety of digital signal processing. The principle and method of using this system are discussed with the basic algorithms of digital signal processing - multiplication and adder - as example. By means of simulation and implementation, it is found that this system has much higher processing speed and efficiency, compared with other kinds of GM multipliers.
引用
收藏
页码：25 / 28
页数：4
相关论文
共 50 条
  • [31] VLSI architecture JDF the reconfigurable computing engine for digital signal processing applications
    Chen, LF
    Lai, YK
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 937 - 940
  • [32] Run-time reconfigurable systems for digital signal processing applications: A survey
    Shoa, A
    Shirani, S
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2005, 39 (03): : 213 - 235
  • [33] Parallelisation of digital signal processing in uniform and reconfigurable filter banks for satellite communications
    Gockler, Heinz G.
    Groth, Alexandra
    Abdulazim, Mohammed N.
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 1059 - +
  • [34] Reconfigurable pipelined 2-D convolvers for fast digital signal processing
    Bosi, B
    Bois, G
    Savaria, Y
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1999, 7 (03) : 299 - 308
  • [35] Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
    Alireza Shoa
    Shahram Shirani
    Journal of VLSI signal processing systems for signal, image and video technology, 2005, 39 : 213 - 235
  • [36] A novel architecture of dynamically reconfigurable fused multiply–adder for digital signal processing
    Tsukahara A.
    Kanasugi A.
    Artificial Life and Robotics, 2014, 19 (3) : 233 - 238
  • [37] Electronic warfare digital signal processing on COTS computer systems with reconfigurable architectures
    Fouts, Douglas J.
    Macklin, Kendrick R.
    Zulaica, Daniel P.
    Duren, Russell W.
    Journal of Aerospace Computing, Information and Communication, 2005, 2 (10): : 414 - 429
  • [38] high-level power optimization for digital signal processing in reconfigurable logic
    Clarke, Jonathan A.
    Constantinides, George A.
    2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2006, : 941 - +
  • [39] Design of Efficient Reconfigurable Digital Compensator for Advanced Wireless Transmitter Using Computational Digital Signal Processing
    Lim, Jonggyun
    Ku, Hyunchul
    CONVERGENCE AND HYBRID INFORMATION TECHNOLOGY, 2011, 206 : 641 - 648
  • [40] Design of efficient reconfigurable digital compensator for advanced wireless transmitter using computational digital signal processing
    Lim, Jonggyun
    Ku, Hyunchul
    Communications in Computer and Information Science, 2011, 206 CCIS : 641 - 648
12345