A novel open-loop high-speed CMOS sample-and-hold

被引：13

作者：

Mousazadeh, Morteza ^{[1
]}

Hadidi, Khayrollah ^{[1
]}

Khoei, Abdollah ^{[1
]}

机构：

[1] Urmia Univ, Microelect Res Lab, Orumiyeh 53139, West Azerbaijan, Iran

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2008年 / 62卷 / 08期

关键词：

sample and hold; ADC; charge injection; linearity;

D O I：

10.1016/j.aeue.2007.08.003

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new open-loop high-speed CMOS sample-and-hold is presented. Based on new method for further reduction of voltage-dependent charge injection, a new CMOS sample-and-hold was designed. Simulation results confirm the effectiveness of this method. Over 10dB improvement in signal-to-noise ratio, compared to the signal-to-noise ratio of conventional bottom plate sampling S/Hs was achieved with this method. A comparison between newly designed S/H and the bottom-plate sampling S/H is presented. (c) 2007 Elsevier GmbH. All rights reserved.

引用

页码：588 / 596

页数：9

共 50 条

[41] DESIGN OF A LOW-POWER HIGH-SPEED COMPARATOR IN 0.13μm CMOS [J].

Fouzy, B. B. A. ;

Reaz, M. B. I. ;

Bhuiyan, M. A. S. ;

Badal, M. T. I. ;

Hashim, F. H. .

2016 INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRICAL, ELECTRONIC AND SYSTEMS ENGINEERING (ICAEES), 2016, :289-292

[42] A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology [J].

Ghasemian, Hossein ;

Ghasemi, Razieh ;

Abiri, Ebrahim ;

Salehi, Mohammad Reza .

MICROELECTRONICS JOURNAL, 2019, 92

[43] High-Speed Multilevel Binary Imaging CMOS Image Sensor for Object Feature Extraction [J].

Lee, Yong-Seok ;

Kim, Hyeon-June .

IEEE SENSORS JOURNAL, 2022, 22 (16) :15934-15943

[44] High-speed cascode cross-coupled CMOS dynamic comparator with auxiliary inverter pair [J].

Krishna, Komala ;

Nambath, Nandakumar .

MICROELECTRONICS JOURNAL, 2024, 149

[45] An on-chip interpolation based readout scheme for low-power, high-speed CMOS image sensors [J].

Kaur, Amandeep ;

Mishra, Deepak ;

Sarkar, Mukul .

2018 IEEE SENSORS, 2018, :633-636

[46] A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20 MS/s and 54-dB S/N at 30 MS/s [J].

Sugimoto, Y .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (04) :696-700

[47] A highly linear and large bandwidth fully differential CMOS line driver suitable for high-speed data transmission applications [J].

Savadi Oskooei, M ;

Hadidi, K ;

Khoei, A .

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2005, E88A (02) :416-423

[48] Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect [J].

Dubey, Avaneesh K. ;

Nagaria, R. K. .

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2019, 28 (09)

[49] Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit [J].

Sawigun, Chutham ;

Serdijn, Wouter A. .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2011, 58 (07) :1615-1626

[50] An Ultra High-Resolution Low Propagation Delay Time and Low Power with 1.25GS/s CMOS Dynamic Latched Comparator For High-Speed SAR ADCs in 180nm Technology [J].

Mandavi, Sina ;

Jafarzadeh, Mahsa ;

Poreh, Maryam ;

Ataei, Shadi .

2017 IEEE 4TH INTERNATIONAL CONFERENCE ON KNOWLEDGE-BASED ENGINEERING AND INNOVATION (KBEI), 2017, :260-265

← 1 2 3 4 5 →