Memory Processing Unit for In-Memory Processing

被引:33
作者
Ben Hur, Rotem [1 ]
Kvatinsky, Shahar [1 ]
机构
[1] Technion Israel Inst Technol, Andrew & Erna Viterbi Fac Elect Engn, IL-3200003 Haifa, Israel
来源
PROCEEDINGS OF THE 2016 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH) | 2016年
关键词
Memristive systems; memristor; logic design; MAGIC; Crossbar memory; memory controller; CPU; MPU; MEMRISTOR;
D O I
10.1145/2950067.2950086
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Performance and energy of modern computers, usually built as von Neumann machines, are primarily limited by data transfer from the memory to the CPU and vice versa. Only a true non-von Neumann architecture, where data is processed and stored within the same unit can remove this bottleneck. Using emerging non-volatile resistive memory technologies (namely, memristors) enables the development of Memory Processing Unit (MPU) - a novel non-von Neumann architecture. MPU relies on adding computing capabilities to the memristive memory cells without changing the basic memory array structure, and is compatible with existing computing systems. This paper describes the MPU architecture and examines its controller.
引用
收藏
页码:171 / 172
页数:2
相关论文
共 9 条
[1]  
[Anonymous], 2015, 2015 International Joint Conference on Neural Networks (IJCNN)
[2]  
Hamdioui S, 2015, DES AUT TEST EUROPE, P1718
[3]   MAGIC-Memristor-Aided Logic [J].
Kvatinsky, Shahar ;
Belousov, Dmitry ;
Liman, Slavik ;
Satat, Guy ;
Wald, Nimrod ;
Friedman, Eby G. ;
Kolodny, Avinoam ;
Weiser, Uri C. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2014, 61 (11) :895-899
[4]   The Desired Memristor for Circuit Designers [J].
Kvatinsky, Shahar ;
Friedman, Eby G. ;
Kolodny, Avinoam ;
Weiser, Uri C. .
IEEE CIRCUITS AND SYSTEMS MAGAZINE, 2013, 13 (02) :17-22
[5]  
Kvatinsky S, 2011, 2011 IEEE 29TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), P142, DOI 10.1109/ICCD.2011.6081389
[6]   Two memristors suffice to compute all Boolean functions [J].
Lehtonen, E. ;
Poikonen, J. H. ;
Laiho, M. .
ELECTRONICS LETTERS, 2010, 46 (03) :230-230
[7]   Recursive Algorithms in Memristive Logic Arrays [J].
Lehtonen, Eero ;
Poikonen, Jussi H. ;
Tissari, Jari ;
Laiho, Mika ;
Koskinen, Lauri .
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2015, 5 (02) :279-292
[8]  
Sheu SS, 2009, SYMP VLSI CIRCUITS, P82
[9]  
Talati N., IEEE T NANOTEC UNPUB