Hybrid Evolutionary Design Space Exploration Algorithm With Defence Against Third Party IP Vulnerabilities

被引:3
作者
Rajmohan, Shathanaa [1 ]
Ramasubramanian, N. [1 ]
Naganathan, Nagi [2 ]
机构
[1] Natl Inst Technol Tiruchirappalli, Dept Comp Sci & Engn, Tiruchirappalli 620015, India
[2] Broadcom Ltd, Allentown, PA 18109 USA
关键词
Trojan horses; Hardware; Space exploration; Integrated circuits; IP networks; Consumer electronics; Redundancy; Design space exploration (DSE); evolutionary algorithm; hardware trojan; high level synthesis (HLS); HARDWARE TROJAN ATTACKS; HIGH-LEVEL SYNTHESIS; GENETIC ALGORITHM; CIRCUITS;
D O I
10.1109/TCAD.2019.2960340
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
With the globalization of the semiconductor industry, the supply chain is fragmented across geographies, which has resulted in the importing of third-party IP cores in designs. Such third party IP cores have increased concerns about hardware Trojans. To address such concerns, development of an effective Trojan detection methodology is crucial. In this article, we present a low-cost Trojan detection and activation prevention mechanism for high level synthesis. In particular, a particle swarm optimization-based design space exploration method is proposed which is combined with a Trojan detection mechanism to minimize resource requirements. Additionally, a hybrid evolutionary algorithm-based Trojan detection method is formed with a novel vendor allocation procedure to find low-cost solutions. The proposed algorithm is compared with existing methods-based on Pareto and non-Pareto-based evaluations to verify their efficiency. From the experiment results, it has been verified that the proposed algorithm offers defence against Trojans similar to existing algorithms with less hardware overhead.
引用
收藏
页码:2602 / 2614
页数:13
相关论文
共 45 条
  • [21] A genetic algorithm for the design space exploration of datapaths during high-level synthesis
    Krishnan, Vyas
    Katkoori, Srinivas
    [J]. IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, 2006, 10 (03) : 213 - 229
  • [22] Efficient and Reliable High-Level Synthesis Design Space Explorer for FPGAs
    Liu, Dong
    Schafer, Benjamin Carrion
    [J]. 2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2016,
  • [23] Meng PF, 2016, DES AUT TEST EUROPE, P918
  • [24] MO-PSE: Adaptive multi-objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor design
    Mishra, Vipul Kumar
    Sengupta, Anirban
    [J]. ADVANCES IN ENGINEERING SOFTWARE, 2014, 67 : 111 - 124
  • [25] Narasimhan S., 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), P71, DOI 10.1109/HST.2011.5954999
  • [26] Office of the Under Secretary of Defense for Acquisition Technology and Logistics, 2005, DEF SCI BOARD TASK F
  • [27] Palesi M, 2002, CODES 2002: PROCEEDINGS OF THE TENTH INTERNATIONAL SYMPOSIUM ON HARDWARE/SOFTWARE CODESIGN, P67, DOI 10.1109/CODES.2002.1003603
  • [28] q Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach
    Rajendran, Jeyavijayan
    Sinanoglu, Ozgur
    Karri, Ramesh
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (09) : 2946 - 2959
  • [29] Reynders N., 2011, 2011 IEEE Asian Solid-State Circuits Conference, P113, DOI 10.1109/ASSCC.2011.6123617
  • [30] Salmani H., 2010, P 2010 IEEE INT WORK, P1