An interface circuit for a Josephson-CMOS hybrid digital system

被引：18

作者：

Suzuki, M ^{[1
]}

Maezawa, M ^{[1
]}

Takato, H ^{[1
]}

Nakagawa, H ^{[1
]}

Hirayama, F ^{[1
]}

Kiryu, S ^{[1
]}

Aoyagi, M ^{[1
]}

Sekigawa, T ^{[1
]}

Shoji, A ^{[1
]}

机构：

[1] Electrotech Lab, Tsukuba, Ibaraki 3058568, Japan

来源：

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY | 1999年 / 9卷 / 02期

关键词：

D O I：

10.1109/77.783738

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For broadband data communication between Josephson and CMOS digital systems, amplification of small Josephson-output signals and synchronization between the systems are important issues. We present an interface circuit for a Josephson-CMOS hybrid digital system. The interface circuit consists of a parallel-in-parallel-out (PIPO) circuit and built-in Josephson-MOS amplifiers. The PIPO circuit, implemented based on 4JL latching logic technology, performs synchronized data transfer between the Josephson and CMOS circuits. The Josephson-MOS amplifiers consists of stacked Josephson junctions (Suzuki stacks) and MOS inverters which are monolithically integrated on a chip. The circuits have been designed, fabricated and tested. We have successfully confirmed correct operation of the circuits.

引用

页码：3314 / 3317

页数：4