A novel online offset-cancellation mechanism in a low-power 6-bit 2GS/s flash-ADC

被引：8
|
作者：
Amini, Abdollah [1 ]
Baradaranrezaeii, Ali [1 ]
Hassanzadazar, Mina [1 ]
机构：
[1] UGI, Dept Microelect Engn, Orumiyeh, Iran
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2019年 / 99卷 / 02期
关键词：
Online offset-cancellation; Bubble error; Relative offset; Flash ADC; High speed; Low power;
D O I：
10.1007/s10470-018-1375-2
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an online offset-cancellation method which is embedding in a low-power 6-bit flash analog to digital converter. A set of low-offset comparators are employed as the first step and then utilizing a novel online method leads to eliminate the effect of the relative offset between all comparators that is the origin of the bubble errors. The offset-cancellation mechanism is based on bulk-driven method where it takes about 0.7 mu s for the bulk nodes to settle down and cancel the relative offset voltage. Simulation results using HSPICE software with standard 0.18 mu m CMOS technology parameters, demonstrate 5.06 ENOB at 2GS/s with the power consumption of 35mW and 0.27FoM.
引用
收藏
页码：219 / 229
页数：11
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