Enabling Side Channel Secure FSMs in the presence of Low Power Requirements

As silicon-based technology feature sizes continue to decrease and designs remain susceptible to novel attacks designers face competing goals when creating secure, low power, integrated circuits (ICs). Often, low power designs rely on heavy minimization and optimization procedures while many secure designs use low-level duplication mechanisms to thwart attacks. An area that requires special attention, and is crucial in both realms, is the power consumption profile of Finite State Machines (FSM). This work specifically addresses the key concern of creating secure, low-power, FSM encodings. This work details a flexible, secure, encoding strategy which, in conjunction with security-based structural modifications, can provide low-power security solutions against side channel attacks. The secure encoding strategy includes methods that modify the original constraints in order to provide varying levels of protection that approach traditional low power encoding methods. Specifically, this work uses the MCNC benchmark suite to compare the state space and encoding requirement for secure (70% increase) and relaxed encoding methods (53-67% increase) aimed at increasing overall device security while reducing state-state transition cost (N-peak = 2).