A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock

This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45 nm SOI technology for validation. At an oscillation frequency of 5.0 GHz, the proposed VCO achieves a phase noise of -120 dBc/Hz at 1 MHz offset, while consuming 1.35 mW. This translates into an FoM of -191 dBc/Hz.