Pass-transistor adiabatic logic using single power-clock supply

被引：137
|
作者：
Oklobdzija, VG [1 ]
Maksimovic, D [1 ]
Lin, FC [1 ]
机构：
[1] UNIV COLORADO,DEPT ELECT & COMP ENGN,BOULDER,CO 80309
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1997年 / 44卷 / 10期
关键词：
adiabatic computing; energy recovery; low power logic;
D O I：
10.1109/82.633443
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present a new pass-transistor adiabatic logic (PAL) that operates from a single power-clock supply and outperforms the previously reported adiabatic logic techniques in terms of its energy use, PAL is a dual-rail logic with relatively low gate complexity: a PAL gate consists of true and complementary NMOS functional blocks, and a pair of cross-coupled PMOS devices. In simulation tests using a standard 1.2 mu CMOS technology, the circuit has been found to operate up to 160 MHz clock frequency and down to 1.5 V peak-to-peak sinusoidal power-clock supply, Operation of a 1600-stage PAL shift register fabricated in the 1.2 mu CMOS technology has been experimentally verified.
引用
收藏
页码：842 / 846
页数：5
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