Definition of dielectric breakdown for ultra thin (<2 nm) gate oxides

The different stages of wear-out of an ultra thin 1.7 nm SiO2 during a time dependent dielectric breakdown test of a poly-Si gate metal-oxide-silicon capacitor structure are discussed. For these ultra thin gate oxides, dielectric breakdown already occurs in the direct tunnelling regime. It is shown that the initial continuous increase of the direct tunnel current during constant Voltage stress is followed by a complex fluctuation mode. This is defined as the dielectric breakdown of these ultra thin (< 2 nm) gate oxide layers and is explained by the formation of a very localised conducting path in the oxide. (C) 1997 Elsevier Science Ltd.