Clock Distribution Networks for 3-D Integrated Circuits

被引：29

作者：

Pavlidis, Vasilis F. ^{[1
]}

Savidis, Ioannis ^{[1
]}

Friedman, Eby G. ^{[1
]}

机构：

[1] Univ Rochester, Dept Elect & Comp Engn, Rochester, NY 14627 USA

来源：

PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2008年

关键词：

D O I：

10.1109/CICC.2008.4672170

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Three-dimensional (3-D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3-D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Experimental results of a 3-D test circuit manufactured by the MIT Lincoln Laboratories are also described. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew and power dissipation measurements for the different clock topologies are also provided.

引用

页码：651 / 654

页数：4

共 13 条

[1]

[Anonymous], 1995, Clock Distribution Networks in VLSI Circuits and Systems

[2]

[Anonymous], FDSOI DES GUID

[3]

[Anonymous], P AS S PAC DES AUT C

[4]

ARUNACHALAM V, 2008, P ACM IEEE INT GREAT

[5] Clocking design and analysis for a 600-MHz alpha microprocessor [J].

Bailey, DW ;

Benschneider, BJ .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (11) :1627-1633

[6] A UNIFIED DESIGN METHODOLOGY FOR CMOS TAPERED BUFFERS [J].

CHERKAUER, BS ;

FRIEDMAN, EG .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1995, 3 (01) :99-111

[7]

Cui W, 2002, APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, P465, DOI 10.1109/APCCAS.2002.1115009

[8] Fabrication of high aspect ratio 35 μm pitch interconnects for next generation 3-D wafer level packaging by through-wafer copper electroplating [J].

Dixit, Pradeep ;

Miao, Jianmin .

56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, :388-+

[9] Clock distribution networks in synchronous digital integrated circuits [J].

Friedman, EG .

PROCEEDINGS OF THE IEEE, 2001, 89 (05) :665-692

[10] CMOS CIRCUIT SPEED AND BUFFER OPTIMIZATION [J].

HEDENSTIERNA, N ;

JEPPSON, KO .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1987, 6 (02) :270-281

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