A Review of Junctionless Transistor Technology and Its Challenges

被引：7

作者：

Kaundal, Shalu ^{[1
]}

Rana, Ashwani Kumar ^{[1
]}

机构：

[1] Natl Inst Technol Hamirpur, Dept Elect & Commun Engn, Hamirpur 177005, HP, India

来源：

JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS | 2019年 / 14卷 / 03期

关键词：

CMOS Technology; Junctionless; MOSFETs; Scaling; Short Channel Effects; HIGH-K SPACER; NANOWIRE TRANSISTOR; INVERSION-MODE; PERFORMANCE ESTIMATION; SILICON NANOWIRE; HIGH LINEARITY; GATE; DESIGN; DEVICE; FET;

D O I：

10.1166/jno.2019.2508

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Researchers are working ardently under downscaling challenges beyond 22 nm technology node. Attaining high chip density without compromising performance is imperative to stay on the scaling trend in MOSFETs. To extend the scaling advantages, Junctionless Transistor (JLT) has been recently introduced as a new concept in the devices. The Junctionless geometry eases the fabrication process and allows continuing downscaling with reduced short channel effects (SCEs) and sub-threshold leakages. This paper reviews the current researches on JLTs and presents its potential and challenges for the forthcoming technologies. Furthermore, this work presented the simulation study of strained engineered junctionless structure.

引用

页码：310 / 320

页数：11

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