A CMOS square-law vector summation circuit

被引：16
作者：
Liu, SI
Chang, CC
机构：
[1] Department of Electrical Engineering, National Taiwan University, Taipei 10664, R.O.C.
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1996年 / 43卷 / 07期
关键词：
D O I：
10.1109/82.508428
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A CMOS vector summation circuit using the square-law characteristics of MOS transistors in the saturation region is presented. Simulation and experimental results are given to verify the theoretical analyzes, Second-order effects such as mobility reduction and transistor mismatch are also investigated, The proposed circuits are expected to be useful in analog signal-processing applications.
引用
收藏
页码：520 / 524
页数：5
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