High density and fully compatible embedded DRAM cell with 45nm MOS technology (CMOS6)

被引：0

作者：

Sanuki, T ^{[1
]}

Sogo, Y ^{[1
]}

Oishi, A ^{[1
]}

Okayama, Y ^{[1
]}

Hasumi, R ^{[1
]}

Morimasa, Y ^{[1
]}

Kinoshita, T ^{[1
]}

Komoda, T ^{[1
]}

Tanaka, H ^{[1
]}

Hiyama, K ^{[1
]}

Komoguchi, T ^{[1
]}

Matsumoto, T ^{[1
]}

Oota, K ^{[1
]}

Yokoyama, T ^{[1
]}

Fukasaku, K ^{[1
]}

Katsumata, R ^{[1
]}

Kido, M ^{[1
]}

Tamura, M ^{[1
]}

Takegawa, Y ^{[1
]}

Yoshimura, H ^{[1
]}

Kasai, K ^{[1
]}

Ohno, K ^{[1
]}

Saito, M ^{[1
]}

Aochi, H ^{[1
]}

Iwai, M ^{[1
]}

Nagashima, N ^{[1
]}

Matsuoka, E ^{[1
]}

Okamoto, Y ^{[1
]}

Noguchi, T ^{[1
]}

机构：

[1] Toshiba Co Ltd, Syst LSI Div, SoC Res & Dev Ctr, Semicond Co,Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

For the first time, a deep trench based embedded DRAM cell for 45nm node system on a chip (SoC) applications is presented. We achieve both high data retention time and full compatibility with logic process, while scaling eDRAM cell down to 0.069 mu m(2) size. In order to compensate the loss of capacitance in aggressively scaled deep trench, high enhancement of storage node capacitance up to 60% is achieved by introducing the bottle etching process with LOCOS collar structure and the high-k node dielectric material (Al2O3). Hybrid STI structure is applied for void free gap filling, and high improvement of retention time is obtained by reduction of induced stress. Ultra Shallow Buried Strap (USBS) structure without silicide block process realizes the integration without any extra process after deep trench formation and extremely low strap resistance. No degradation of retention characteristics is observed by introducing Ni silicide on the top of storage node junction. Disposable sidewall spacer and Flash Lamp Anneal, which are key technologies of logic transistor, are also applied to eDRAM cell successfully. In addition, high functional test yield up to 61% has been obtained for 256Kb ADM.

引用

页码：14 / 15

页数：2

共 5 条

[1]

Iwai M, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P12

[2]

MATSUBARA Y, 2003, IEDM, P426

[3] A high performance 100 nm generation SOC technology [CMOS IV] for high density embedded memory and mixed signal LSIs [J].

Miyashita, K ;

Nakayama, T ;

Oishi, A ;

Hasumi, R ;

Owada, M ;

Aota, S ;

Okayama, Y ;

Matsumoto, M ;

Igarashi, H ;

Yoshida, T ;

Kasai, K ;

Yoshitomi, T ;

Fukaura, Y ;

Kawasaki, H ;

Ishimaru, K ;

Adachi, K ;

Fujiwara, M ;

Ohuchi, K ;

Takayanagi, M ;

Oyamatsu, H ;

Matsuoka, F ;

Noguchi, T ;

Kakumu, M .

2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2001, :11-12

[4]

Oishi A, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P166

[5]

OTA K, 2005, UNPUB S VLSI TECH

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