Analytical drain current and threshold voltage model and device design of short-channel Si nanowire transistors

被引：0

作者：

Tanaka, Chika ^{[1
]}

Hagishima, Daisuke ^{[1
]}

Uchida, Ken ^{[1
,2
]}

Numata, Toshinori ^{[1
]}

机构：

[1] Toshiba Co Ltd, Corp Res & Dev Ctr, Adv LSI Technol Lab, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

[2] Keio Univ, Tokyo 108, Japan

来源：

SOLID-STATE ELECTRONICS | 2013年 / 86卷

关键词：

Silicon nanowire transistor; Threshold voltage; Analytical model; GATE;

D O I：

10.1016/j.sse.2013.04.022

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Device design for cylindrical Si nanowire field-effect-transistors is studied in short channel regime of 22 nm technology generations and beyond. A two-dimensional quasi-analytical model reveals that a critical minimum channel length is 1.5 times as long as a Si nanowire diameter to suppress the short channel effects. The quantum mechanical effect due to the structural carrier confinement in nanowire with narrow diameter deteriorates both the threshold voltage roll-offs and the subthreshold characteristics. (C) 2013 Elsevier Ltd. All rights reserved.

引用

页码：27 / 31

页数：5

共 21 条

[1] Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's [J].