Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique

被引:10
|
作者
Hwang, Yin-Tsung [1 ]
Lin, Jin-Fa [2 ]
机构
[1] Natl Chung Hsing Univ, Dept Elect Engn, Taichung 40227, Taiwan
[2] Chaoyang Univ Technol, Dept Informat & Commun Engn, Taichung 41349, Taiwan
关键词
Extended true-single-phase-clock flip flops (E-TSPC FF); low power; low voltage; prescaler; FREQUENCY-SYNTHESIZER; HIGH-SPEED; PRESCALER; OPTIMIZATION; DIVIDER;
D O I
10.1109/TVLSI.2011.2161598
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
An extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for low supply voltage and low power consumption applications is presented. By using a wired OR scheme; only one transistor is needed to implement both the counting logic and the mode selection control. This can enhance the working frequency of the counter due to a reduced critical path between the E-TSPC flip flops (FFs). Since the number of transistor stacking between the power rails is kept at merely two, the proposed design is sustainable to low V-DD operations (531 MHz at 0.6 V V-DD) for the power saving purpose. Simulation results show that compared with two classic E-TSPC based designs in 0.18 mu m process technology, as much as 16.4% in operation speed and 39% in power-delay-product can be achieved by the proposed design.
引用
收藏
页码:1738 / 1742
页数:5
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