Reducing clock skew variability via crosslinks

被引:19
作者
Rajaram, Anand [1 ]
Hu, Jiang
Mahapatra, Rabi
机构
[1] Texas Instruments Inc, Dallas, TX 75243 USA
[2] Texas A&M Univ, Dept Elect Engn, College Stn, TX 77843 USA
[3] Texas A&M Univ, Dept Comp Sci, College Stn, TX 77843 USA
关键词
clock; skew; variability; very large scale integration (VLSI);
D O I
10.1109/TCAD.2005.855928
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amounts of wirelength. This paper suggests to construct a low-cost nontree clock network by inserting crosslinks in a given clock tree. The effects of the link insertion on clock skew variability are analyzed. Based on the analysis, this paper proposes two link insertion schemes that can quickly convert a clock tree to a nontree with significantly lower skew variability and very limited wirelength increase. In these schemes, the complicated nontree delay computation is circumvented. Further, they can be applied to the recently popular nonzero skew routing easily. The effectiveness of the proposed techniques has been validated through SPICE-based Monte Carlo simulations.
引用
收藏
页码:1176 / 1182
页数:7
相关论文
共 21 条
[1]   NEAR-OPTIMAL CRITICAL SINK ROUTING TREE CONSTRUCTIONS [J].
BOESE, KD ;
KAHNG, AB ;
MCCOY, BA ;
ROBINS, G .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (12) :1417-1436
[2]   COMPUTING SIGNAL DELAY IN GENERAL RC-NETWORKS BY TREE LINK PARTITIONING [J].
CHAN, PK ;
KARPLUS, K .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1990, 9 (08) :898-902
[3]   ZERO SKEW CLOCK ROUTING WITH MINIMUM WIRELENGTH [J].
CHAO, TH ;
HSU, YC ;
HO, JM ;
BOESE, KD ;
KAHNG, AB .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (11) :799-814
[4]   A simple yet effective merging scheme for prescribed-skew clock routing [J].
Chaturvedi, R ;
Hu, J .
21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, :282-287
[5]  
Cong J., 1998, ACM Transactions on Design Automation of Electronic Systems, V3, P341, DOI 10.1145/293625.293628
[6]   CLOCK SKEW OPTIMIZATION [J].
FISHBURN, JP .
IEEE TRANSACTIONS ON COMPUTERS, 1990, 39 (07) :945-951
[7]   A multigigahertz clocking scheme for the Pentium® 4 microprocessor [J].
Kurd, NA ;
Barkatullah, JS ;
Dizon, RO ;
Fletcher, TD ;
Madland, PD .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (11) :1647-1653
[8]   Power supply noise suppression via clock skew scheduling [J].
Lam, WCD ;
Koh, CK ;
Tsao, CWA .
PROCEEDING OF THE 2002 3RD INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2002, :355-360
[9]  
LIN S, 1994, IEEE IC CAD, P284
[10]   Impact of interconnect variations on the clock skew of a gigahertz microprocessor [J].
Liu, Y ;
Nassif, SR ;
Pileggi, LT ;
Strojwas, AJ .
37TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2000, 2000, :168-171