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Chemical vapor deposition of monolayer MoS2 directly on ultrathin Al2O3 for low-power electronics
被引:77
|作者:
Bergeron, Hadallia
[1
]
Sangwan, Vinod K.
[1
]
McMorrow, Julian J.
[1
]
Campbell, Gavin P.
[1
]
Balla, Itamar
[1
]
Liu, Xiaolong
[2
]
Bedzyk, Michael J.
[1
,2
,3
]
Marks, Tobin J.
[1
,4
]
Hersam, Mark C.
[1
,2
,4
,5
]
机构:
[1] Northwestern Univ, Dept Mat Sci & Engn, Evanston, IL 60208 USA
[2] Northwestern Univ, Appl Phys Grad Program, Evanston, IL 60208 USA
[3] Northwestern Univ, Dept Phys & Astron, Evanston, IL 60208 USA
[4] Northwestern Univ, Dept Chem, Evanston, IL 60208 USA
[5] Northwestern Univ, Dept Elect Engn & Comp Sci, Evanston, IL 60208 USA
基金:
美国国家航空航天局;
加拿大自然科学与工程研究理事会;
美国国家科学基金会;
关键词:
FIELD-EFFECT TRANSISTORS;
ATOMIC LAYER DEPOSITION;
MOLYBDENUM-DISULFIDE;
HIGH-MOBILITY;
TRANSPORT-PROPERTIES;
PHASE GROWTH;
LARGE-SCALE;
CIRCUITS;
UNIFORM;
FILMS;
D O I:
10.1063/1.4975064
中图分类号:
O59 [应用物理学];
学科分类号:
摘要:
Monolayer MoS2 has recently been identified as a promising material for high-performance electronics. However, monolayer MoS2 must be integrated with ultrathin high-j gate dielectrics in order to realize practical low-power devices. In this letter, we report the chemical vapor deposition (CVD) of monolayer MoS2 directly on 20 nm thick Al2O3 grown by atomic layer deposition (ALD). The quality of the resulting MoS2 is characterized by a comprehensive set of microscopic and spectroscopic techniques. Furthermore, a low-temperature (200 degrees C) Al2O3 ALD process is developed that maintains dielectric integrity following the high-temperature CVD of MoS2 (800 degrees C). Field-effect transistors (FETs) derived from these MoS2/Al2O3 stacks show minimal hysteresis with a sub-threshold swing as low as similar to 220mV/decade, threshold voltages of similar to 2V, and current I-ON/I-OFF ratio as high as similar to 10 4, where I-OFF is defined as the current at zero gate voltage as is customary for determining power consumption in complementary logic circuits. The system presented here concurrently optimizes multiple low-power electronics figures of merit while providing a transfer-free method of integrating monolayer MoS2 with ultrathin high-j dielectrics, thus enabling a scalable pathway for enhancement-mode FETs for low-power applications.
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