Strained Si channel NMOSFETs using a stress field with Si1-yCy source and drain stressors

被引:4
作者
Chang, S. T. [1 ]
Tasi, H. -S. [1 ]
Kung, C. Y. [1 ]
机构
[1] Natl Chung Hsing Univ, Dept Elect Engn, Taichung 402, Taiwan
关键词
strained Si; mobility; SiC; stressor;
D O I
10.1016/j.tsf.2005.09.197
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The strain field in the silicon channel of a metal-oxide-semiconductor transistor with silicon-carbon alloy source and drain stressors was evaluated using the commercial process simulator FLOOPS-ISE (TM). The physical origin of the strain components in the transistor channel region was explained. The magnitude and distribution of the strain components, and their dependence on device design parameters such as the spacing L-G between the silicon-carbon alloy stressors, the carbon mole fraction in the stressors; and stressor depth were investigated. Reducing the stressor spacing L-G or increasing the carbon mole fraction in the stressors and stressor depth increases the magnitude of the vertical compressive stress and the lateral tensile stress in the portion of the N channel region where the inversion charge resides. This is beneficial for improving the electron mobility in n-channel metal-oxide-semiconductor transistors. A simple guiding principle for an optimum combination of the above-mentioned device design parameters in terms of mobility enhancement, drain current enhancement and the tradeoff consideration for junction leakage current degradation. (c) 2005 Elsevier B.V. All rights reserved.
引用
收藏
页码:333 / 337
页数:5
相关论文
共 11 条
[1]  
ANG KW, 2004, IEDM TECHN DIG, P12
[2]   STRAIN EFFECTS ON DEVICE CHARACTERISTICS - IMPLEMENTATION IN DRIFT-DIFFUSION SIMULATORS [J].
EGLEY, JL ;
CHIDAMBARRAO, D .
SOLID-STATE ELECTRONICS, 1993, 36 (12) :1653-1664
[3]  
GE CH, 2003, TECHN DIG INT EL DEV, P73
[4]  
Ghani T., 2003, TECHN DIG INT EL DEV, V2003, P978
[5]  
*ISE TCAD TOOLS, 2004, DESSIS FLOOPS ISE US, V10
[7]  
KUMAGAI Y, 2002, INT C SOL STAT DEV M, P14
[8]   Strained SiNMOSFETs for high performance CMOS technology [J].
Rim, K ;
Koester, S ;
Hargrove, M ;
Chu, J ;
Mooney, PM ;
Ott, J ;
Kanarsky, T ;
Ronsheim, P ;
Ieong, M ;
Grill, A ;
Wong, HSP .
2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2001, :59-60
[9]  
Shimizu A., 2001, TECHN DIG INT EL DEV, P433
[10]   A logic nanotechnology featuring strained-silicon [J].
Thompson, SE ;
Armstrong, M ;
Auth, C ;
Cea, S ;
Chau, R ;
Glass, G ;
Hoffman, T ;
Klaus, J ;
Ma, ZY ;
Mcintyre, B ;
Murthy, A ;
Obradovic, B ;
Shifren, L ;
Sivakumar, S ;
Tyagi, S ;
Ghani, T ;
Mistry, K ;
Bohr, M ;
El-Mansy, Y .
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (04) :191-193