High-Performance Junctionless MOSFETs for Ultralow-Power Analog/RF Applications

被引：90
作者：
Ghosh, Dipankar [1 ]
Parihar, Mukta Singh [1 ]
Armstrong, G. Alastair [2 ]
Kranti, Abhinav [1 ]
机构：
[1] Indian Inst Technol Indore, Low Power Nanoelect Res Grp, Elect Engn Discipline, Indore 452017, Madhya Pradesh, India
[2] Queens Univ Belfast, Sch Elect Elect Engn & Comp Sci, Belfast BT9 5AH, Antrim, North Ireland
来源：
IEEE ELECTRON DEVICE LETTERS | 2012年 / 33卷 / 10期
关键词：
Analog/RF; double-gate MOSFET; junctionless (JL) transistor; ultralow power (ULP); underlap source/drain (S/D); SOI MOSFETS; FINFETS;
D O I：
10.1109/LED.2012.2210535
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this letter, we demonstrate the usefulness of ultralow-power (ULP) junctionless (JL) MOSFETs in achieving improved analog/RF metrics as compared to nonunderlap and underlap MOSFETs. At a drain current (I-ds) of 10 mu A/mu m, JL devices achieve two times higher values of cutoff frequency (f(T)) and maximum oscillation frequency (f(MAX)) along with 65% improvement in voltage gain (A(VO)) in comparison to conventional nonunderlap MOSFETs. ULP JL devices, which do not require source/drain (S/D) profile optimization, can perform comparably to underlap devices, thereby relaxing the stringent process constraints associated with S/D profile optimization in nanoscale devices. The results highlight new opportunities for realizing future ULP analog/RF design with JL transistors.
引用
收藏
页码：1477 / 1479
页数：3
相关论文
共 12 条
[1]  
Anderson B A., 2006, US patent, Patent No. [7009265 B2, 7009265]
[2]  
[Anonymous], ATLAS US MAN
[3]  
[Anonymous], 2010, P 34 EUR SOL STAT DE
[4]   RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs [J].
Cho, Seongjae ;
Kim, Kyung Rok ;
Park, Byung-Gook ;
Kang, In Man .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (05) :1388-1396
[5]  
Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]
[6]   Quantum-mechanical effects in trigate SOI MOSFETs [J].
Colinge, JP ;
Alderman, JC ;
Xiong, WZ ;
Cleavelin, CR .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (05) :1131-1136
[7]   What are the limiting parameters of deep-submicron MOSFETs for high frequency applications? [J].
Dambrine, G ;
Raynaud, C ;
Lederer, D ;
Dehan, M ;
Rozeaux, O ;
Vanmackelberg, M ;
Danneville, F ;
Lepilliet, S ;
Raskin, JP .
IEEE ELECTRON DEVICE LETTERS, 2003, 24 (03) :189-191
[8]   Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications [J].
Kranti, A ;
Chung, TM ;
Flandre, D ;
Raskin, JP .
SOLID-STATE ELECTRONICS, 2004, 48 (06) :947-959
[9]   Junctionless 6T SRAM cell [J].
Kranti, A. ;
Lee, C. -W. ;
Ferain, I. ;
Yan, R. ;
Akhavan, N. ;
Razavi, P. ;
Yu, R. ;
Armstrong, G. A. ;
Colinge, J. -P. .
ELECTRONICS LETTERS, 2010, 46 (22) :1491-1492
[10]   Design and optimization of FinFETs for ultra-low-voltage analog applications [J].
Kranti, Abhinav ;
Armstrong, G. Alastair .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (12) :3308-3316
12