A modified decimation filter design for oversampled sigma delta A/D converters

被引：0

作者：

Lei, C ^{[1
]}

Zhao, YF ^{[1
]}

Gao, DY ^{[1
]}

Wu, W ^{[1
]}

Wang, ZM ^{[1
]}

Zhu, XF ^{[1
]}

Peng, HP ^{[1
]}

机构：

[1] Northwestern Polytech Univ, Aviat Microelect Ctr, Xian 710072, Peoples R China

来源：

2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2 | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper presents a novel lower power polyphase transformable stage non-recursive comb (PTSNC) filter architecture considering the area and power consumption, which is very suitable for high-order oversampled sigma delta A/D converters. The proposed decimation filter has 1/3 less hardware and power compared to conventional non-recursive decimation filters when the filter was implemented using 0.6-mu m CMOS standard when the circuit work clock was 100MHz.

引用

页码：294 / 297

页数：4