High-speed hardware architectures of the Whirlpool hash function

被引：7

作者：

McLoone, M ^{[1
]}

McIvor, C ^{[1
]}

Savage, A ^{[1
]}

机构：

[1] Queens Univ Belfast, Inst Elect Commun & Informat Technol, Belfast, Antrim, North Ireland

来源：

FPT 05: 2005 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/FPT.2005.1568539

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

High-speed hardware architectures of the Whirlpool hash function are presented in this paper. A full Look-Up Table (LUT) based design is shown to be the fastest method by; which to implement the non-linear layer of the algorithm in terms of logic. An iterative Whirlpool architecture implemented on the Virtex X4VLX100 device runs at 4.79 Gbps, while an unrolled architecture achieves a throughput of 4.9 Gbps. This is faster than a SHA-512 design implemented on the same device and other previously reported hash function architectures.

引用

页码：147 / 153

页数：7

共 16 条

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