Circuit techniques in a 266-MHz MMX-enabled processor

被引:12
作者
Draper, D
Crowley, M
Holst, J
Favor, G
Schoy, A
Trull, J
BenMeir, A
Khanna, R
Wendell, D
Krishna, R
Nolan, J
Mallick, D
Partovi, H
Roberts, M
Johnson, M
Lee, T
机构
[1] Advanced Micro Devices, Inc., Sunnyvale
[2] Transmeta Corp., Santa Clara
[3] Stanford University, Center for Integrated System, Stanford
[4] University of British Columbia, Vancouver, BC
[5] Carleton University, Ottawa, Ont.
[6] Bell Northern Research, Ottawa
[7] American Microsystems, CA
[8] Fairchild Intergraph Adv. Proc. Div., Clipper Microprocessor
[9] Advanced Micro Devices, Sunnyvale, CA
[10] University of Illinois, Urbana-Champaign, IL
[11] Amdahl Corporation, Fremont, CA
[12] NexGen, AMD, Milpitas, CA
[13] AMD, Sunnyvale, CA
[14] University of Iowa, Iowa City, IA
[15] Memory Design Group, United Technologies MOSTEK, Carrollton, TX
[16] UNISYS, Blue Bell, PA
[17] AMD, Milpitas, CA
[18] California Institute of Technology, Pasadena, CA
基金
美国国家科学基金会;
关键词
cache memories; computer architecture; design automation software; flip-flops; integrated circuit design; logic design; phase-locked loops; programmable logic array; read only memories;
D O I
10.1109/4.641685
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The AMD-K6 MMX-enabled processor is plug-compatible with the industry-standard Socket 7 and is binary compatible with the existing base of legacy X86 software. The microarchitecture is based on an out-of-order, superscalar execution engine using speculative execution, High performance and compact die size are achieved by using self-resetting, self-timed and pulsed-latch circuit design techniques in custom blocks and placed-and-routed blocks of standard cells, The 162 sq, mm die is fabricated on a 0.35-mu m, five-layer metal process with local interconnect, It is assembled into a ceramic pin grid array (PGA) using C4 flip-chip mounting. The processor functions at clock speeds up to 266 MHz.
引用
收藏
页码:1650 / 1664
页数:15
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