In this paper novel designs of half-adder cells using CNFETs for high speed applications are proposed. These designs increase speed by decreasing the number of transistors along with their critical path. The threshold voltage of a CNFET is controlled by its chirality, therefore utilizing this feature in the proposed designs leads to a reduction in the number of transistors. HSPICE simulations demonstrate that the proposed half-adder cells achieve significant performance. CNFET transistors are combined with capacitor networks with the aim of increasing speed.