Silicon wafer requirements for ULSI device processing

被引:3
作者
Illuzzi, F [1 ]
机构
[1] ST Microelect Srl, IT-20041 Agrate Brianza, MI, Italy
来源
GETTERING AND DEFECT ENGINEERING IN SEMICONDUCTOR TECHNOLOGY | 2002年 / 82-84卷
关键词
COPs; CZ growth; epitaxial wafers; silicon;
D O I
10.4028/www.scientific.net/SSP.82-84.1
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
With the increasing integration density towards the sub-half micron devices, the design rules reduce up to 0.12 mum and below. Therefore the requirements for the base materials of the integrated circuits such as the silicon wafers are constantly rinsing. Along with the reduction of the structure size, a change in the wafer diameter is also occurring and some semiconductors companies are getting ready to move from 200 mm. wafer to 300 mm wafers technology to enhance the batch size of chips per wafer. On average every three years a new generation of memories devices has been introduced, the number of transistors per integrated circuit increases four times every three years, which is also known in literature as Moore's law, published in 1965. Therefore semiconductor devices present stringent requests for more pure silicon.
引用
收藏
页码:1 / 6
页数:6
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