A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient

被引：4

作者：

Hsieh, Cheng-En ^{[1
]}

Liu, Shen-Iuan ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 10667, Taiwan

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2019年 / 27卷 / 03期

关键词：

Analog-to-digital converter (ADC); frequency drift; frequency drift compensator (FDC); phase-locked loop (PLL); reference spur; CMOS;

D O I：

10.1109/TVLSI.2018.2880477

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A frequency-drift-compensated phase-locked loop (PLL) with an LC voltage-controlled oscillator (VCO) is fabricated in TSMC 40-nm CMOS process. The proposed frequency drift compensator employs an analog-to-digital converter to monitor the control voltage of the PLL in background. The capacitor banks are adjusted to compensate for the frequency drift of the LC-VCO. The measured reference spur is -65.15 dBc. The measured best phase noise of this PLL is -108.32 and -130.26 dBc/Hz at the frequency offset of 1 and 10 MHz, respectively, among five chips. This chip occupies 0.223-mm(2) active area. The power dissipation of this PLL is 6.32 mW from a 0.9-V supply voltage. The average temperature coefficient is 2.43 ppm/degrees C from 20 degrees C to 100 degrees C.

引用

页码：501 / 510

页数：10