Circuit design techniques for on-chip power supply noise monitoring system

被引：0

作者：

Chen, H ^{[1
]}

Hsu, L

机构：

[1] IBM Res Div, Yorktown Hts, NY 10598 USA

[2] IBM Syst & Technol Grp, Hopewell Jct, NY 12533 USA

来源：

INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2005年 / 3728卷

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the novel design of an on-chip noise-monitoring device, which can measure the power supply noise of each individual macro and determine the noise interference between different macros. A hierarchical noise-monitoring system is proposed to monitor and store the power supply noise information for core-based design, as part of the built-in-self-test system. The method can be further extended from system-on-chip to system-on-package to provide a complete coverage of noise testing methodology. The circuit of a properly-sized noise monitor has been simulated with the actual VDD and GND noise waveforms of a 4-GHz benchmark microprocessor to verify its functionality.

引用

页码：704 / 713

页数：10

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