Physical demonstration of polymorphic self-checking circuits

被引:40
作者
Ruzicka, Richard [1 ]
Sekanina, Lukas [1 ]
Prokop, Roman
机构
[1] Brno Univ Technol, Fac Informat Technol, Brno 61266, Czech Republic
来源
14TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS | 2008年
关键词
D O I
10.1109/IOLTS.2008.23
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NANDINOR gate controlled by Vdd is presented. This gate was fabricated and utilized in a self-checking polymorphic adder. This paper presents an experimental evaluation of this novel implementation.
引用
收藏
页码:31 / 36
页数:6
相关论文
共 21 条
  • [1] [Anonymous], 2006, EVOLVABLE HARDWARE
  • [2] [Anonymous], NASA TECH BRIEFS
  • [3] DIAZ M, 1979, IEEE T COMPUT, V28, P276, DOI 10.1109/TC.1979.1675338
  • [4] FRANK MP, 1999, THESIS MIT
  • [5] GARVIE M, 2005, THESIS U SUSSEX
  • [6] Designing polymorphic circuits with polymorphic gates: a general design approach
    Luo, W.
    Zhang, Z.
    Wang, X.
    [J]. IET CIRCUITS DEVICES & SYSTEMS, 2007, 1 (06) : 470 - 476
  • [7] Partially duplicated code-disjoint carry-skip adder
    Marienfeld, D
    Ocheretnij, V
    Gössel, M
    Sogomonyan, ES
    [J]. 17TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2002, : 78 - 86
  • [8] Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits
    Ocheretnij, V
    Marienfeld, D
    Sogomonyan, ES
    Gössel, M
    [J]. 10TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS, 2004, : 31 - 36
  • [9] Feasibility study of designing TSC sequential circuits with 100% fault coverage
    Piestrak, SJ
    [J]. 17TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2002, : 354 - 362
  • [10] Pradhan D. K., 1996, FAULT TOLERANT COMPU