Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting

被引:17
作者
Sengupta, Anirban [1 ]
Rathor, Mahendra [1 ]
机构
[1] IIT Indore, Discipline Comp Sci & Engn, Indore 453552, India
关键词
Biometrics (access control); Hardware; IP networks; Cryptography; Consumer electronics; Digital signatures; Biometric fingerprint; consumer electronics~(CEs); hardware accelerator; intellectual property (IP) protection; security; 1; IP CORE; PROTECTION;
D O I
10.1109/TVLSI.2020.2999514
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This article presents a novel methodology to secure hardware accelerators (such as digital signal processing (DSP) and multimedia intellectual property (IP) cores) against ownership threats/IP piracy using biometric fingerprinting. In this approach, an IP vendor's biometric fingerprint is first converted into a corresponding digital template, followed by embedding fingerprint's digital template into the design in the form of secret biometric constraints; thereby generating a secured hardware accelerator design. The results report the following qualitative and quantitative analysis of the proposed biometric fingerprint approach: 1) impact of 11 different fingerprints on probability of coincidence (Pc) metric. As evident, the proposed approach achieves a very low Pc value in the range of 2.22E-3 to 4.35E-6. Further, the biometric fingerprint achieves total constraints size between minimum 350 bits to maximum 895 bits; 2) impact of six different resource constraints on the design cost overhead of JPEG compression hardware postembedding biometric fingerprint. As evident, for all the resource constraints implemented, the design cost overhead is 0%; and 3) comparative analysis of proposed biometric fingerprint with recent work, for five different signature strength values, in terms of Pc. As evident, the proposed approach achieves minimum 3.9E+2 times and maximum 6.9E+4 times lower Pc, when compared to recent work.
引用
收藏
页码:1979 / 1992
页数:14
相关论文
共 27 条
[1]  
Alilou V.K., 2020, FINGERPRINT MATCHING
[2]  
[Anonymous], 2020, 15 NM OPEN CELL LIB
[3]   IPP@HDL: Efficient intellectual property protection scheme for IP cores [J].
Castillo, Encarnacion ;
Meyer-Baese, Uwe ;
Garcia, Antonio ;
Parrilla, Luis ;
Lloris, Antonio .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (05) :578-591
[4]   HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection [J].
Chakraborty, Rajat Subhra ;
Bhunia, Swarup .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, 28 (10) :1493-1502
[5]   IP protection of DSP algorithms for system on chip implementation [J].
Chapman, R ;
Durrani, TS .
IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2000, 48 (03) :854-861
[6]   Survey of hardware protection of design data for integrated circuits and intellectual properties [J].
Colombier, Brice ;
Bossuet, Lilian .
IET COMPUTERS AND DIGITAL TECHNIQUES, 2014, 8 (06) :274-287
[7]  
Hong I., 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), P849, DOI 10.1109/DAC.1999.782161
[8]   Behavioral synthesis techniques for intellectual property protection [J].
Koushanfar, F ;
Hong, IK ;
Potkonjak, M .
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2005, 10 (03) :523-545
[9]   Obfuscating DSP Circuits via High-Level Transformations [J].
Lao, Yingjie ;
Parhi, Keshab K. .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (05) :819-830
[10]  
Le Gal Bertrand, 2011, 2011 IEEE 9th International New Circuits and Systems Conference (NEWCAS 2011), P490, DOI 10.1109/NEWCAS.2011.5981326