On Improved Verification of Reconfigurable Real-Time Systems

被引:5
作者
Hafidi, Yousra [1 ,2 ,3 ,4 ]
Kahloul, Laid [3 ]
Khalgui, Mohamed [1 ,2 ]
Ramdani, Mohamed [1 ,2 ,3 ,4 ]
机构
[1] Univ Carthage, Natl Inst Appl Sci & Technol, LISI Lab, Tunis 1080, Tunisia
[2] Jinan Univ, Sch Elect & Informat Engn, Jinan, Shandong, Peoples R China
[3] Biskra Univ, Comp Sci Dept, LINFI Lab, Biskra, Algeria
[4] Univ Tunis El Manar, Tunis, Tunisia
来源
PROCEEDINGS OF THE 14TH INTERNATIONAL CONFERENCE ON EVALUATION OF NOVEL APPROACHES TO SOFTWARE ENGINEERING (ENASE) | 2019年
关键词
Real-time System; Reconfiguration; Formal verification; Model-checking; CTL;
D O I
10.5220/0007736603940401
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
This paper deals with formal modeling and verification of reconfigurable real-time systems under reconfigurability and real-time constraints. To deal with the modeling, we enrich the formalism, named reconfigurable timed net condition event systems (R-TNCESs), with new reconfiguration forms such as the ability to update the earliest/latest firing time on the intervals which are associated to flow arcs. To handle the verification of the new extended formalism, an algorithm is defined to generate a timed accessibility graph for timed net condition event systems (TNCESs). We control the verification complexity of R-TNCESs using a new method which accelerate the generation of accessibility graphs, where redundancies, repetitions, and unnecessary computations are avoided as much as possible. An experimentation is carried out and a performance evaluation is achieved to demonstrate the advantages of the proposed contribution compared with related works.
引用
收藏
页码:394 / 401
页数:8
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