Accurate Performance Evaluation for the Horizontal Nanosheet Standard-Cell Design Space Beyond 7nm Technology

被引：0

作者：

Lee, Y. M. ^{[1
]}

Na, M. H. ^{[1
]}

Chu, A. ^{[1
]}

Young, A. ^{[1
]}

Hook, T. ^{[1
]}

Liebmann, L. ^{[3
]}

Nowak, E. J. ^{[3
]}

Baek, S. H. ^{[2
]}

Sengupta, R. ^{[2
]}

Trombley, H. ^{[1
]}

Miao, X. ^{[1
]}

机构：

[1] IBM Res, Albany, NY 12203 USA

[2] Samsung Elect, Albany, NY USA

[3] GLOBALFOUNDRIES Inc, Albany, NY USA

来源：

2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Vertically-stacked horizontal gate-all-around (GAA) Nanosheet structures have been recognized as good candidates for beyond the 7nm technology node to achieve improved power-performance and area scaling compared to FinFET technologies. Full realization of device-performance entitlement in high-performance and high-density chip designs is, therefore, of critical importance. In this paper, we present a quantitative performance evaluation of horizontal Nanosheet structures focused on key design styles as well as unique Nanosheet challenges such as gate-resistance. This analysis was performed with a fully developed design kit over a wide range of sub-7nm design, including various cell heights, as well as design features such as M1 power staples and performance-aware designs for smaller track cells.

引用

页数：4