An Ultra-Low Phase-Noise Ka-Band Tunable Frequency Synthesizer

This paper presents a Ka-band, fractional-N phase-locked loop (PLL) for use in radar applications. The PLL, with a tuning range of 31.7-36.0 GHz, utilizes a high-speed Sigma-Delta Sigma Delta modulator to enable the fractional division. To achieve a step size of less than 200 MHz with ultra-low in-band phase noise, a high-frequency 2.6 GHz reference signal is used with 4-bits of fractional frequency control. To reduce 1/f noise, bipolar transistors are used almost exclusively within the PLL signal path, including the phase detector, loop filter, VCO, and multimodulus divider with three cascaded 2/3 dividers that give an overall divide range of 8-15. The PLL chip is fabricated in a 0.13 mu m SiGe BiCMOS process, measures 2.03 x 1.85 mm(2), and consumes 220 mA, 46 mA, and 7 mA from a 4.5 V, 3.0 V, and 1.5 V power supply, respectively, for a total power consumption of 1.1 W. The phase noise is measured to be -120.4dBc/Hz at 1 MHz offset from the carrier, and is limited by the reference signal for offset frequencies below 1 MHz.