3D Integration of CMOS transistors with ICV-SLID technology

被引：27

作者：

Wieland, R ^{[1
]}

Bonfert, D ^{[1
]}

Klumpp, A ^{[1
]}

Merkel, R ^{[1
]}

Nebrich, L ^{[1
]}

Weber, J ^{[1
]}

Ramm, P ^{[1
]}

机构：

[1] Fraunhofer Inst Reliabil & Microintegrat, Munich Div, D-80686 Munich, Germany

来源：

MICROELECTRONIC ENGINEERING | 2005年 / 82卷 / 3-4期

关键词：

3D integration; CMOS; ICV-SLID; wafer thinning; bonding;

D O I：

10.1016/j.mee.2005.07.052

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

3D Integration of CMOS transistors with ICV-SLID technology is reported in this paper. NMOS and PMOS metal gate transistor devices have been further processed by forming deep trench inter-chip-vias and by thinning the substrate to 25 mu m remaining silicon thickness. No degradation of transistor behavior found due to the additional M-processing steps. Results of the process flow and electrical measurements of transistors on thin silicon are shown in this paper. (c) 2005 Published by Elsevier B.V.

引用

页码：529 / 533

页数：5