EFFICIENT PARALLEL PATH CHECKING FOR LINEAR-TIME TEMPORAL LOGIC WITH PAST AND BOUNDS

被引:8
作者
Kuhtz, Lars [1 ]
Finkbeiner, Bernd [1 ]
机构
[1] Univ Saarland, D-66123 Saarbrucken, Germany
关键词
linear-time temporal logic (LTL); linear-time temporal logic with past; bounded temporal operators; model checking; path checking; parallel complexity; COMPLEXITY; ALGORITHM;
D O I
10.2168/LMCS-8(4:10)2012
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Path checking, the special case of the model checking problem where the model under consideration is a single path, plays an important role in monitoring, testing, and verification. We prove that for linear-time temporal logic (LTL), path checking can be efficiently parallelized. In addition to the core logic, we consider the extensions of LTL with bounded-future (BLTL) and past-time (LTL+Past) operators. Even though both extensions improve the succinctness of the logic exponentially, path checking remains efficiently parallelizable: Our algorithm for LTL, LTL+Past, and BLTL+Past is in AC(1) (logDCFL) subset of NC.
引用
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页数:24
相关论文
共 31 条
[1]   A SIMPLE PARALLEL TREE CONTRACTION ALGORITHM [J].
ABRAHAMSON, K ;
DADOUN, N ;
KIRKPATRICK, DG ;
PRZYTYCKA, T .
JOURNAL OF ALGORITHMS, 1989, 10 (02) :287-302
[2]  
[Anonymous], 2000, DCAGRS
[3]  
[Anonymous], 1990, Handbook of Theoretical Computer Science, Volume A: Algorithms and Complexity
[4]  
ARMONI R, 2006, LNCS
[5]   Combining test case generation and runtime verification [J].
Artho, C ;
Barringer, H ;
Goldberg, A ;
Havelund, K ;
Khurshid, S ;
Lowry, M ;
Pasareanu, C ;
Rosu, G ;
Sen, K ;
Visser, W ;
Washington, R .
THEORETICAL COMPUTER SCIENCE, 2005, 336 (2-3) :209-234
[6]   On monotone planar circuits [J].
Barrington, DAM ;
Lu, CJ ;
Miltersen, PB ;
Skyum, S .
FOURTEENTH ANNUAL IEEE CONFERENCE ON COMPUTATIONAL COMPLEXITY, PROCEEDINGS, 1999, :24-31
[7]   Automata-based assertion-checker synthesis of PSL properties [J].
Boule, Marc ;
Zilic, Zeljko .
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2008, 13 (01)
[8]  
Chakraborty T, 2006, LECT NOTES COMPUT SC, V4337, P57
[9]   Combining system level modeling with assertion based verification [J].
Dahan, A ;
Geist, D ;
Gluhovsky, L ;
Pidan, D ;
Shapir, G ;
Wolfsthal, Y .
6th International Symposium on Quality Electronic Design, Proceedings, 2005, :310-315
[10]   AN NC ALGORITHM FOR EVALUATING MONOTONE PLANAR CIRCUITS [J].
DELCHER, AL ;
KOSARAJU, SR .
SIAM JOURNAL ON COMPUTING, 1995, 24 (02) :369-375