A low power 24 GHz LNA in 0.13 μm CMOS

This paper presents a 24 GHz differential LNA in 0.13 mu m CMOS technology. It is based on a combined NMOS/PMOS transconductor allowing DC-current reuse. A gain of 14 dB and a noise figure of 5 dB have been achieved at the center frequency. The circuit exhibits input-referred I dB compression point and IIP3 of -14.1 dBm and -1.7 dBm, respectively. Due to implementation of the virtual ground concept high ESD protection is provided at the RF pins without degrading the high-frequency performance. The measured TLP and HBM ESD robustness is 2 A and 2.5 kV, respectively. The LNA consumes only 12 mA from a single 1.5 V supply. The chip size including the pads is 0.23 mm(2).