Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D+IC

被引:0
作者
Yang, Chih-Chao [1 ]
Chiu, Kuan-Chang [2 ]
Chou, Cheng-Tse [2 ]
Liao, Chang-Ning [2 ]
Chuang, Meng-Hsi [2 ]
Hsieh, Tung-Ying [1 ]
Huang, Wen-Hsien [1 ]
Shen, Chang-Hong [1 ]
Shieh, Jia-Min [1 ]
Yeh, Wen-Kuan [1 ]
Chen, Yu-Hsiu [3 ]
Wu, Meng-Chyi [3 ]
Lee, Yi-Hsien [2 ]
机构
[1] Natl Nano Device Labs, Hsinchu, Taiwan
[2] Natl Tsing Hua Univ, Dept Mat Sci & Engn, Hsinchu, Taiwan
[3] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu, Taiwan
来源
2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY | 2016年
关键词
monolithic; 3D; monolayer; TMD; image sensor; 3DIC;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A monolithic 3D image sensor is demonstrated by sequentially fabricating large-area (> 2cmx2cm) monolayer (<1nm) transition metal dichalcogenide (TMD) phototransistor array on top of a 3D logic/memory hybrid 3D(+)IC connected by high density interconnect. The photocurrent of the monolayer MoS2 phototransistor shows a linear response to the incident laser power density and exhibits high responsivity (>20A/W). The bottom 3D stackable poly-Si nanowire FET, fabricated by low thermal budget process (T-sub< 400 degrees C), represents steep subthreshold swing (< 120mV/dec.) and high driving current (> 200uA/um). The low driving voltage 6T SRAM shows a static noise margin (SNM) of 150 mV at V-DD= 0.5V. Such integration of large-area monolayer TMD phototransistor array on logic/memory hybrid 3D(+)IC enables the low power and low cost monolithic 3D image sensor.
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页数:2
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