Design of Practical Parity Generator and Parity Checker Circuits in QCA

Quantum-dot Cellular Automata (QCA) has emerged as a possible alternative to CMOS in recent era of nanotechnology. Some attractive features of QCA include extremely low power consumption and dissipation, high device packing density, high speed (in order of THz). QCA based design of common digital modules have been studied extensively in recent past. Parity generator and parity checker circuits play important role in error detection and hence, act as essential components in communication circuits. However, very few efforts have been made for efficient design of QCA based parity generator and checker circuits so far. Moreover, these existing designs lack in practical realizability as they compromise a lot with commonly accepted design metrics such as area, delay, complexity, and cost of fabrication. This paper presents new designs of parity generator and parity checker circuits in QCA which outperform all the existing designs in terms of above mentioned metrics. The proposed designs can also be easily extended to handle large number of inputs with a linear increase in area and latency.