Thermo-Mechanical and Electrical Characterization of Through-Silicon Vias with a Vapor Deposited Polyimide Dielectric Liner

A study using a vapor deposited polyimide (VDP) dielectric liner to electrically isolate through-silicon vias (TSVs) has demonstrated electrical and thermo-mechanical performance superior to sub-atmospheric chemically vapor deposited (SACVD) tetraethyl orthosilicate (TEOS) liner in 5 mu m x 50 mu m TSVs. The VDP liner is continuous and highly conformal, with a worst-case coverage of 85% relative to the target deposition thickness. Moreover, the material integrates through TSV metallization, anneal, and polish. Electrically, VDP provides lower inter-via capacitance than the more conventional SACVD TEOS liner. Mechanically, blanket film stress of VDP measured as a function of temperature shows no hysteresis up to 400 degrees C and a stress delta during cycling of only 45 MPa. The delta is an order of magnitude lower than SACVD TEOS. The thermo-mechanical behavior of VDP also results in a lower residual stress in the silicon area surrounding the structure, which enables a smaller keep-away zone for TSVs and effectively increases the density of transistors in silicon for 3D integrated systems.