A 16-channel digital TDC chip

被引:6
作者
Bailly, P
Chauveau, J
Genat, JF
Huppert, JF
Lebbolo, H
Roos, L
Zhang, B
机构
[1] Univ Paris 06, LPNHE, F-75252 Paris, France
[2] Univ Paris 07, F-75252 Paris, France
关键词
D O I
10.1016/S0168-9002(99)00459-3
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
A 16-channel digital TDC chip has been built for the DIRC Cherenkov counter of the BaBar experiment at the SLAG B-factory (Stanford, USA). The binning is 0.5 ns and the full-scale 32 ms. The data-driven architecture integrates channel buffering and selective readout of data falling within a programmable time window. The linearity is better than 80 ps r.m.s. on 90% of the production parts. (C) 1999 Elsevier Science B.V. All rights reserved.
引用
收藏
页码:432 / 437
页数:6
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