Design of Efficient Reversible Multiplier

被引：0

作者：

Rangaraju, H. G. ^{[1
]}

Suresh, Aakash Babu ^{[2
]}

Muralidhara, K. N. ^{[3
]}

机构：

[1] Govt Engn Coll, Dept Elect & Commun Engn, Chamarajanagar 571313, India

[2] Robert Bosch Engn & Business Solut Ltd, Bangalore 560095, Karnataka, India

[3] PES Coll Engn, Dept Elect & Commun Engn, Mandya 571401, India

来源：

ADVANCES IN COMPUTING AND INFORMATION TECHNOLOGY, VOL 3 | 2013年 / 178卷

关键词：

Reversible Gate; Reversible Logic; Constant/Garbage Input; Garbage Output; Quantum Cost; Reversible Multiplier; LOGIC;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Reversible logic is emerging computing paradigm with applications in Ultra-low power Nano computing, quantum computing, Low power CMOS design, Optical Information Processing, Bioinformatics etc. In this paper, the 4x4 reversible multiplier circuit is proposed with the design of new reversible gate called RAM. The proposed multiplier circuit is efficient compared to the existing designs in terms of gate counts, garbage outputs, constant inputs and quantum cost. The design can be generalized to construct NxN reversible multiplier circuit.

引用

页码：571 / +

页数：2

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