Specifications of Nanoscale Devices and Circuits for Neuromorphic Computational Systems

被引:132
作者
Rajendran, Bipin [1 ]
Liu, Yong [1 ]
Seo, Jae-sun [1 ]
Gopalakrishnan, Kailash [1 ]
Chang, Leland [1 ]
Friedman, Daniel J. [1 ]
Ritter, Mark B. [1 ]
机构
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
关键词
CMOS; hybrid integrated circuits; neural network hardware; resistive random access memory (RRAM); NEURONS;
D O I
10.1109/TED.2012.2227969
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations.
引用
收藏
页码:246 / 253
页数:8
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