Symmetrical Buffered Clock-Tree Synthesis with Supply-Voltage Alignment

For high-performance synchronous systems, nonuniform/non-ideal supply voltages of buffers (e.g., due to IR-drop) may incur a large clock skew and thus serious performance degradation. This paper addresses this problem and presents the first symmetrical buffered clock-tree synthesis flow that considers supply voltage differences of buffers. We employ a two-phase technique of bottom-up clock sink clustering to determine the tree topology, followed by top-down buffer placement and wire routing to complete the clock tree. At each level of processing, clock skew and wirelength are minimized by the determination of buffer embedding regions and the alignment of buffer supply voltages. Experimental results show that our method can reach, on average, respective 76% and 40% clock skew reduction compared to the state-of-the-art work (1) without supply voltage consideration and (2) with an extension for supply voltages based on our top-down flow. The reduction is achieved by marginal resource and runtime overheads. Note that our method can meet the stringent skew constraint set by the 2010 ISPD contest for all cases, while other counterparts cannot. In particular, our work provides a key insight into the importance of handling practical design issues (such as IR-drop) for real-world clock-tree synthesis.