The Impact of Charge Collection Volume and Parasitic Capacitance on SEUs in SOI- and Bulk-FinFET D Flip-Flops

被引：19

作者：

Ball, D. R. ^{[1
]}

Alles, M. L. ^{[1
]}

Kauppila, J. S. ^{[1
]}

Harrington, R. C. ^{[1
]}

Maharrey, J. A. ^{[1
]}

Nsengiyumva, P. ^{[1
]}

Haeffner, T. D. ^{[1
]}

Rowe, J. D. ^{[1
]}

Sternberg, A. L. ^{[1
]}

Zhang, E. X. ^{[1
]}

Bhuva, B. L. ^{[1
]}

Massengill, L. W. ^{[1
]}

机构：

[1] Vanderbilt Univ, Dept Elect Engn & Comp Sci, 221 Kirkland Hall, Nashville, TN 37235 USA

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2018年 / 65卷 / 01期

关键词：

Bulk; D flip-flop (DFF); FinFET; fully depleted silicon on insulator (FDSOI); nanowire; parasitic capacitance effects; SOI; single event (SE); SE transient (SET); SE upset (SEU); ADVANCED TECHNOLOGY NODES;

D O I：

10.1109/TNS.2017.2784763

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Measured single-event (SE) heavy-ion data for comparable silicon on insulator (SOI) and bulk silicon FinFET D flip-flop (DFF) designs demonstrate a notably greater difference between the SOI and bulk responses, which has commonly been observed. Data show greater than 30x in SE upset (SEU) LET threshold and 3 orders of magnitude decrease in saturated SE cross section for SOI FinFETs when compared to bulk FinFETs. The difference in SEU threshold is shown to be due to the saturation of SE transient (SET) pulsewidths at values that are comparable to feedback-loop delays of DFF design in the SOI technology. The feedback-loop delays in FinFET technologies are significantly impacted by the inherent parasitic capacitance. For the bulk technology, SET pulsewidths do not saturate due to charge collection from the substrate region.

引用

页码：326 / 330

页数：5