Implementation and Evaluation of Power Consumption of an Iris Pre-processing Algorithm on Modern FPGA

被引：0

作者：

Blasinsky, Henryk ^{[1
]}

Amiel, Frederic ^{[1
]}

Ea, Thomas ^{[1
]}

Rossant, Florence ^{[1
]}

Mikovicova, Beata ^{[1
]}

机构：

[1] Inst Super Elect Paris, F-75006 Paris, France

来源：

RADIOENGINEERING | 2008年 / 17卷 / 04期

关键词：

FPGA; power optimization; dilation; erosion; general purpose processor; SoPC;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this article, the efficiency and applicability of several power reduction techniques applied on a modern 65nm FPGA is described. For image erosion and dilation algorithms, two major solutions were tested and compared with respect to power and energy consumption. Firstly the algorithm was run on a general purpose processor (gpp) NIOS and then hardware architecture of an Intellectual Property (IP) was designed. Furthermore IPs design was improved by applying a number of power optimization techniques. They involved RTL level clock gating, power driven synthesis with fitting and appropriate coding style. Results show that hardware implementation is much more energy efficient than a general purpose processor and power optimization schemes can reduce the overall power consumption on an FPGA.

引用

页码：108 / 112

页数：5