An Improved Phase Locked Loop Detection Method based on a Novel Dual Second-order Generalized Integrator under Unbalanced Grid Conditions

被引:0
作者
Guo, Jian [1 ]
Wu, Dongjian [2 ]
Si, Jiawen [1 ]
Sun, Yongliang [1 ]
Khan, Roaidar [1 ]
机构
[1] Harbin Engn Univ, Coll Mech & Elect Engn, Harbin 150001, Peoples R China
[2] Harbin Engn Univ, Sch Foreign Studies, Harbin 150001, Peoples R China
来源
2022 41ST CHINESE CONTROL CONFERENCE (CCC) | 2022年
关键词
Dual Second-order Generalized Integrator; Synchronous Reference Frame Phase; locked Loop; Positive Sequence Calculator Module; Phase-locked Loop; FREQUENCY;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Aiming at the problems of grid frequency oscillation and phase distortion in the traditional synchronous reference frame phase-locked loop(SRF-PLL) method for detecting three-phase asymmetric power grid fault signals, an improved PLL method based on a novel dual second-order generalized integratoris proposed. The fundamental voltage component and its 90 degree phase shift component can be extracted by using the novel dual second-order generalized integrator (DSOGI), and then the two orthogonal voltage components are generated. Through the positive sequence calculator (pSC), the positive sequence voltage component is obtained and the disturbance influence caused by the negative sequence component can also be avoided. Meanwhile, in order to eliminate the AC component of the positive voltage component, the low pass filter (LPF) module is used before the positive sequence voltage component enters the phase locked loop (PLL) module. Through simulation and experimental verification, the proposed improved PLL detection method based on the novel DSOGI has proven to perform better than the traditional SRF-PLL both for rapidity and accuracy on detecting the frequency and phase of unbalanced power grid.
引用
收藏
页码:6047 / 6053
页数:7
相关论文
共 10 条
[1]  
[Anonymous], 2018, P CSEE
[2]   Effect of sampling frequency and harmonics on delay-based phase-sequence estimation method [J].
Bongiorno, Massimo ;
Svensson, Jan ;
Sannino, Ambra .
IEEE TRANSACTIONS ON POWER DELIVERY, 2008, 23 (03) :1664-1672
[3]   Three-Phase PLLs With Fast Postfault Retracking and Steady-State Rejection of Voltage Unbalance and Harmonics by Means of Lead Compensation [J].
Freijedo, Francisco D. ;
Yepes, Alejandro G. ;
Lopez, Oscar ;
Vidal, Ana ;
Doval-Gandoy, Jesus .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2011, 26 (01) :85-97
[4]   A Critical Examination of Frequency-Fixed Second-Order Generalized Integrator-Based Phase-Locked Loops [J].
Golestan, Saeed ;
Mousazadeh, Seyyed Yousef ;
Guerrero, Josep M. ;
Vasquez, Juan C. .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2017, 32 (09) :6666-6672
[5]   A Generalized Design Framework of Notch Filter Based Frequency-Locked Loop for Three-Phase Grid Voltage [J].
He, Xiuqiang ;
Geng, Hua ;
Yang, Geng .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2018, 65 (09) :7072-7084
[6]   Practical implementation of delayed signal cancellation method for phase-sequence separation [J].
Svensson, Jan ;
Bongiorno, Massimo ;
Sannino, Ambra .
IEEE TRANSACTIONS ON POWER DELIVERY, 2007, 22 (01) :18-26
[7]  
Wang Y B., 2021, ELECT ELECT, P52
[8]  
[徐海亮 Xu Hailiang], 2012, [电力系统自动化, Automation of Electric Power Systems], V36, P90
[9]  
Yang R.Z., 2021, MACHINERY ELECT, V39, P12
[10]  
[周鹏 Zhou Feng], 2008, [电工技术学报, Transactions of China Electrotechnical Society], V23, P108