Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit

被引：9

作者：

Arnold, Oliver ^{[1
]}

Noethen, Benedikt ^{[1
]}

Fettweis, Gerhard ^{[1
]}

机构：

[1] Dresden Univ Technol TU Dresden, Dresden, Germany

来源：

2012 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI) | 2012年

关键词：

dynamic task scheduling; heterogeneous MPSoC; instruction set extension;

D O I：

10.1109/ISVLSI.2012.51

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper a heterogeneous Multiprocessor System-on-Chip (MPSoC) is controlled by a dynamic task scheduling unit called CoreManager. The instruction set architecture of this unit is extended to improve performance for dynamic data dependency checking, task scheduling, processing element (PE) allocation and data transfer management. In order to analyze and compare different implementations and trade-offs a tool flow was developed. Area and timing results are provided as well. A significant performance improvement can be shown for all parts of the CoreManager.

引用

页码：249 / 254

页数：6