Modeling the backoff strategies of access to shared-memory multiprocessors

Consideration is given to a multiprocessor hierarchical architecture where the stations constituted by processor modules interconnected by a common bus are in turn connected by a ring-shaped system. To access a remote memory module, the processor passes a request via the interconnection system. If the required memory module is busy, then the request is rejected and the time of communication system is wasted. To reduce the time losses in the common bus of a multiprocessor station, the present publication proposes and models the backoff strategies for control of access to the shared memory. Using queueing theory and equilibrium analysis, we develop an approximate model of a generalized backoff strategy and a method for its analysis, which an based on realistic assumptions and enable one to evaluate the efficiency of the generalized strategy with low computational effort.