All-digital phase locked loop for clock recovery

被引：0

作者：

Wei, H ^{[1
]}

Cheng, T ^{[1
]}

机构：

[1] Beijing Jiaotong Univ, Sch Elect & Informat Engn, Beijing, Peoples R China

来源：

ICEMI 2005: Conference Proceedings of the Seventh International Conference on Electronic Measurement & Instruments, Vol 3 | 2005年

关键词：

phase locked loop; FPGA; clock and data recovery circuit;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A first-order all-digital phase locked loop for clock recovery is presented in this paper. The circuit is realized by EP1K50QC208-3, which is a kind of FPGA made by ALTERA, and all the components of the circuit are described by VHDL language. It has been demonstrated that the circuit can recover clock correctly by the simulation and hardware experiment. The circuit is simple, versatile, and suitable for VLSI design and well represented the advantages of the digitalization. So it can be used in the VLSI as an IP core.

引用

页码：395 / 398

页数：4

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