CONSTRUCTION OF PARALLELIZED-DECODING LDPC CODES

被引:0
作者
Wu, Tsung-Che [1 ]
Lee, Chang-Ming
Wang, Cheng-Kuei
机构
[1] Natl Chung Cheng Univ, Dept Commun Engn, Chiayi, Taiwan
来源
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2016年
关键词
LDPC codes; code construction; large girth; parallelization; PARITY-CHECK CODES; MATRICES; DESIGN;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In the parallelization for high-throughput applications, the number of independent memory access usually dominates the coding throughput. Moreover, a class of large-girth low-density parity check (LDPC) codes usually has difficulties to realize the parallelization in the decoder. To cope with these obstacles, we propose an efficient code construction to take the number of required parallel decoding unit and the large-girth constraint into considerations at once. First, the parity check matrix would be split into the block-wise structure to fit the parallelization in the decoder. Second, the conversion of the cycle-checking inequalities can transform the girth issue into a linear system. Finally, based on the decomposition of the polyhedral set, the Smith normal form can efficiently solve inequalities of the proposed system. Simulation results show that the proposed code construction can satisfy the requirements of parallelization and high-performance coding with girth g = 12.
引用
收藏
页码:425 / 428
页数:4
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