Omitting cache look-up for high-performance, low-power microprocessors

被引：0

作者：

Inoue, K ^{[1
]}

Moshnyaga, VG

Murakami, K

机构：

[1] Fukuoka Univ, Dept Elect & Comp Sci, Kasuga, Fukuoka 8140133, Japan

[2] Kyushu Univ, Dept Informat, Kasuga, Fukuoka 8168580, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2002年 / E85C卷 / 02期

关键词：

cache; low power; look up; run time;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache." The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.

引用

页码：279 / 287

页数：9

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